1. Field of the Invention
The present invention relates to a semiconductor integrated device and a method of providing shield interconnection therein.
2. Description of the Related Art
As LSIs have become larger in scale because of a recent advancement of microfabrication in the semiconductor process, it has been possible to provide both a digital signal processing circuit and an analog circuit in a single chip. Inside this circuit where the analog circuit and the digital circuit coexist, an interconnection line for an analog signal required to be highly accurate and an interconnection line for a binary digital signal operating at high frequencies may be provided next to each other, so that a noise interference channel caused by the capacitance between the analog signal line and the digital signal line may exist. In particular, digital signals usually have an amplitude of several volts and perform high-speed transition. Accordingly, noise is mixed into the analog signal line through the capacitance between the analog signal line and the digital signal line, thus causing a problem in that the analog signal cannot be processed with accuracy. Therefore, in semiconductor integrated devices in which an analog circuit susceptible to noise and a high-frequency digital circuit coexist, an attempt has been made to avoid inconvenience such as malfunction due to noise by designing interconnection (providing a layout) so that a first interconnection layer formed of a digital signal line (a high-frequency signal line) and a second interconnection layer formed of an analog signal line cross each other with only an interlayer insulating film therebetween, or the first interconnection layer and the second interconnection layer are totally separated so as not to cross each other.
Further, Japanese Laid-Open Patent Application No. 5-47943 (hereinafter, JP5-47943) discloses a conventional semiconductor integrated device having a multi-interconnection-layer configuration, wherein a first interconnection layer (analog signal interconnection pattern) and a second interconnection layer (digital signal interconnection pattern) are provided; a third interconnection layer is disposed between the first interconnection layer and the second interconnection layer at the intersection thereof; a fourth interconnection layer is disposed below the first interconnection layer; each of the third interconnection layer and the fourth interconnection layer (shield interconnection) is larger in area than the interconnection area part of the first interconnection layer and the second interconnection layer; a contact connecting the third interconnection layer and the fourth interconnection layer is provided on each side of the first interconnection layer; and each of the third interconnection layer and the fourth interconnection layer is provided with a fixed potential. This is known as an interconnection design (layout) method to reduce noise caused on an analog signal line by a digital signal line.
However, according to the conventional semiconductor integrated device disclosed in JP5-47943, there is a problem in that if a circuit element (for example, an output buffer) driving a signal transmitted through the first interconnection layer or the second interconnection layer (for example, a digital signal) has high driving capability, the potential of the third interconnection layer serving as a shield interconnection layer varies by way of electromagnetic induction, so that noise is mixed into the analog signal line provided in the first interconnection layer through the capacitance between the signal interconnection patterns of the second and third interconnection layers and the capacitance between the signal interconnection patterns of the third and first interconnection layers. Further, with respect to the interclock skew of a multi-phase clock signal generated by PLL (Phase Locked Loop), the difference in parasitic capacitance between clock signal lines is a problem in particular. Further, as a result of recent progress in process microfabrication, clock signals operate at a frequency of several GHz. Accordingly, the output buffer increases its driving capability in order to transmit this high-frequency clock signal, thus making it necessary to consider effects on other signal lines.